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STL120NH02V
N-channel 20V - 0.0025 - 120A - PowerFLATTM (6x5) STripFETTM III Power MOSFET
Target Specification
General features
Type STL120NH02V VDSS 20V RDS(on) <0.003 ID 28A(1)
1. Value limited by wire bonding
Improved die-to-footprint ratio Very low profile package (1mm max) Very low thermal resistance Conduction losses reduced 2.5V gate drive Switching losses reduced Very low threshold device
(Chip scale package)
Description
The STL120NH02V utilizes the latest advanced design rules of ST's proprietary STripFETTM Technology. Thanks to a very low threshold, it is ideal for Synchronous Buck Converter in point of load brick module. The Chip-scaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STL120NH02V Marking L120NH02V Package PowerFLATTM (6x5) Packaging Tape & reel
September 2006
Rev 2
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This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
Contents
STL120NH02V
Contents
1 2 3 4 5 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuit ................................................ 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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STL120NH02V
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID ID IDM (1) ID(2) PTOT(2) PTOT(3)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Drain current (continuous) at TC = 25C Total dissipation at TC = 25C Total dissipation at TC = 25C Derating factor Value 20 8 120 75 480 28 100 4 0.03 -55 to 175 Unit V V A A A A W W W/C C
Tj Tstg
2.
Operating junction temperature storage temperature
1. Pulse width limited by safe operating area When mounted on FR-4 board of 1in, 2oz Cu. t<10sec 3. The value is rated according Rthj-C.
Table 2.
Rthj-case
Thermal data
Thermal resistance junction-case (drain) (Steady state) 1.56 31.2 C/W C/W
Rthj-pcb(1) Thermal resistance junction-pcb max
1. When mounted on FR-4 board of 1in, 2oz Cu. t<10sec
Table 3.
Symbol IAR EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max value 10 TBD Unit A mJ
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Electrical characteristics
STL120NH02V
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS =0 VDS = max rating VDS =max rating, TC = 125C VGS = 8V VDS = VGS, ID = 250A VGS = 4.5V, ID = 14A VGS = 2.5V, ID = 14A 0.60 0.0025 0.003 0.003 0.004 Min. 20 1 10 100 Typ. Max. Unit V A A nA V
IDSS
IGSS VGS(th) RDS(on)
Table 5.
Symbol gfs (1) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 16V, ID = 14A Min. Typ. TBD TBD TBD TBD TBD TBD TBD TBD 33 TBD TBD 44 Max. Unit S pF pF pF ns ns ns ns nC nC nC
VDS = 25V, f = 1MHz, VGS = 0
VDD = 10V, ID = 14A RG = 4.7 VGS = 4.5V (see Figure 1) VDD = 10V, ID = 28A, VGS = 2.5V, RG = 4.7 (see Figure 2) f=1MHz Gate DC Bias =0 Test Signal Level =20mV Open Drain
RG
Gate Input Resistance
1.8
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
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STL120NH02V
Electrical characteristics
Table 6.
Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 28A, VGS = 0 TBD TBD TBD TBD TBD TBD Test conditions Min. Typ. Max. 28 112 TBD Unit A A V ns nC A ns nC A
Reverse recovery time ISD = 28A, di/dt = 100A/s, Reverse recovery charge VDD = 16V Reverse recovery current (see Figure 3) Reverse recovery time ISD = 28A, di/dt = 100A/s, Reverse recovery charge VDD = 16V, Tj = 150C Reverse recovery current (see Figure 3)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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Test circuit
STL120NH02V
3
Figure 1.
Test circuit
Switching times test circuit for resistive load Figure 2. Gate charge test circuit
Figure 3.
Test circuit for inductive load Figure 4. switching and diode recovery times
Unclamped Inductive load test circuit
Figure 5.
Unclamped inductive waveform
Figure 6.
Switching time waveform
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STL120NH02V
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STL120NH02V
PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
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STL120NH02V
Revision history
5
Revision history
Table 7.
Date 24-Jun-2005 04-Sep-2006
Revision history
Revision 1 2 New document New template, no content change Changes
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STL120NH02V
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